Nanowire lithography on silicon.

Abstract

Nanowire lithography (NWL) uses nanowires (NWs), grown and assembled by chemical methods, as etch masks to transfer their one-dimensional morphology to an underlying substrate. Here, we show that SiO2 NWs are a simple and compatible system to implement NWL on crystalline silicon and fabricate a wide range of architectures and devices. Planar field-effect transistors made of a single SOI-NW channel exhibit a contact resistance below 20 kOmega and scale with the channel width. Further, we assess the electrical response of NW networks obtained using a mask of SiO2 NWs ink-jetted from solution. The resulting conformal network etched into the underlying wafer is monolithic, with single-crystalline bulk junctions; thus no difference in conductivity is seen between a direct NW bridge and a percolating network. We also extend the potential of NWL into the third dimension, by using a periodic undercutting that produces an array of vertically stacked NWs from a single NW mask.