Graphene-Transition Metal Dichalcogenide Heterojunctions for Scalable and Low-Power Complementary Integrated Circuits.
basic_science · Level V
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- Record sourced from PubMed, PMID 31904930.
- Also identified by DOI 10.1021/acsnano.9b08288.
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Abstract
The most pressing barrier for the development of advanced electronics based on two-dimensional (2D) layered semiconductors stems from the lack of site-selective synthesis of complementary n- and p-channels with low contact resistance. Here, we report an in-plane epitaxial route for the growth of interlaced 2D semiconductor monolayers using chemical vapor deposition with a gas-confined scheme, in which patterned graphene (Gr) serves as a guiding template for site-selective growth of Gr-WS<sub>2</sub>-Gr and Gr-WSe<sub>2</sub>-Gr heterostructures. The Gr/2D semiconductor interface exhibits a transparent contact with a nearly ideal pinning factor of 0.95 for the n-channel WS<sub>2</sub> and 0.92 for the p-channel WSe<sub>2</sub>. The effective depinning of the Fermi level gives an ultralow contact resistance of 0.75 and 1.20 kΩ·μm for WS<sub>2</sub> and WSe<sub>2</sub>, respectively. Integrated logic circuits including inverter, NAND gate, static random access memory, and five-stage ring oscillator are constructed using the complementary Gr-WS<sub>2</sub>-Gr-WSe<sub>2</sub>-Gr heterojunctions as a fundamental building block, featuring the prominent performance metrics of high operation frequency (>0.2 GHz), low-power consumption, large noise margins, and high operational stability. The technology presented here provides a speculative look at the electronic circuitry built on atomic-scale semiconductors in the near future.