Hardware architecture for real-time EEG-based functional brain connectivity parameter extraction.

Abstract

<i>Objective</i>. Design a novel architecture for real-time quantitative characterization of functional brain connectivity (FC) networks derived from wearable electroencephalogram (EEG).<i>Approach</i>. We performed an algorithm to architecture mapping for the calculation of phase lag index to form the functional connectivity networks and the extraction of a set of graph-theoretic parameters to quantitatively characterize these networks. This mapping was optimized using approximations in the mathematical definitions of the algorithms which reduce its computational complexity and produce a more hardware amenable implementation.<i>Main results</i>. The architecture was developed for a 19-channel EEG system. The system can calculate all the functional connectivity parameters in a total time of 131 <i>µ</i>s, utilizes 71% of the total logic resources in the FPGA, and shows 51.84 mW dynamic power consumption at 22.16 MHz operation frequency when implemented in a Stratix IV EP4SGX230K FPGA. Our analysis also showed that the system occupies an area equivalent to approximately 937 K 2-input NAND gates, with an estimated power consumption of 39.3 mW at 0.9 V supply using a 90 nm CMOS application specific integrated circuit technology.<i>Significance</i>. The proposed architecture can calculate the FC and extract the graph-theoretic parameters in real-time with low power consumption. This characteristic makes the architecture ideal for applications such as a wearable closed-loop neurofeedback systems, where constant monitoring of the brain activity and fast processing of EEG is necessary to control the appropriate feedback.