Self-Selective Multi-Terminal Memtransistor Crossbar Array for In-Memory Computing.
basic_science · Level V
Where this comes from
- Record sourced from PubMed, PMID 33443417.
- Also identified by DOI 10.1021/acsnano.0c09441.
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Abstract
Two-terminal resistive switching devices are commonly plagued with longstanding scientific issues including interdevice variability and sneak current that lead to computational errors and high-power consumption. This necessitates the integration of a separate selector in a one-transistor-one-RRAM (1T-1R) configuration to mitigate crosstalk issue, which compromises circuit footprint. Here, we demonstrate a multi-terminal memtransistor crossbar array with increased parallelism in programming <i>via</i> independent gate control, which allows <i>in situ</i> computation at a dense cell size of 3-4.5 F<sup>2</sup> and a minimal sneak current of 0.1 nA. Moreover, a low switching energy of 20 fJ/bit is achieved at a voltage of merely 0.42 V. The architecture is capable of performing multiply-and-accumulate operation, a core computing task for pattern classification. A high MNIST recognition accuracy of 96.87% is simulated owing to the linear synaptic plasticity. Such computing paradigm is deemed revolutionary toward enabling data-centric applications in artificial intelligence and Internet-of-things.