Van der Waals engineering of ferroelectric heterostructures for long-retention memory.
basic_science · Level V
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- Record sourced from PubMed, PMID 33597507.
- Also identified by DOI 10.1038/s41467-021-21320-2 and PMC identifier 7889872.
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Abstract
The limited memory retention for a ferroelectric field-effect transistor has prevented the commercialization of its nonvolatile memory potential using the commercially available ferroelectrics. Here, we show a long-retention ferroelectric transistor memory cell featuring a metal-ferroelectric-metal-insulator-semiconductor architecture built from all van der Waals single crystals. Our device exhibits 17 mV dec<sup>-1</sup> operation, a memory window larger than 3.8 V, and program/erase ratio greater than 10<sup>7</sup>. Thanks to the trap-free interfaces and the minimized depolarization effects via van der Waals engineering, more than 10<sup>4</sup> cycles endurance, a 10-year memory retention and sub-5 μs program/erase speed are achieved. A single pulse as short as 100 ns is enough for polarization reversal, and a 4-bit/cell operation of a van der Waals ferroelectric transistor is demonstrated under a 100 ns pulse train. These device characteristics suggest that van der Waals engineering is a promising direction to improve ferroelectronic memory performance and reliability for future applications.