Self-rectifying resistive memory in passive crossbar arrays.
basic_science · Level V
Where this comes from
- Record sourced from PubMed, PMID 34016978.
- Also identified by DOI 10.1038/s41467-021-23180-2 and PMC identifier 8137934.
- Licence recorded as CC BY.
- The licence permits redistribution, so the abstract is shown in full and the full text is available from the publisher.
Abstract
Conventional computing architectures are poor suited to the unique workload demands of deep learning, which has led to a surge in interest in memory-centric computing. Herein, a trilayer (Hf<sub>0.8</sub>Si<sub>0.2</sub>O<sub>2</sub>/Al<sub>2</sub>O<sub>3</sub>/Hf<sub>0.5</sub>Si<sub>0.5</sub>O<sub>2</sub>)-based self-rectifying resistive memory cell (SRMC) that exhibits (i) large selectivity (ca. 10<sup>4</sup>), (ii) two-bit operation, (iii) low read power (4 and 0.8 nW for low and high resistance states, respectively), (iv) read latency (<10 μs), (v) excellent non-volatility (data retention >10<sup>4</sup> s at 85 °C), and (vi) complementary metal-oxide-semiconductor compatibility (maximum supply voltage ≤5 V) is introduced, which outperforms previously reported SRMCs. These characteristics render the SRMC highly suitable for the main memory for memory-centric computing which can improve deep learning acceleration. Furthermore, the low programming power (ca. 18 nW), latency (100 μs), and endurance (>10<sup>6</sup>) highlight the energy-efficiency and highly reliable random-access memory of our SRMC. The feasible operation of individual SRMCs in passive crossbar arrays of different sizes (30 × 30, 160 × 160, and 320 × 320) is attributed to the large asymmetry and nonlinearity in the current-voltage behavior of the proposed SRMC, verifying its potential for application in large-scale and high-density non-volatile memory for memory-centric computing.