Reconfigurable Logic-in-Memory Computing Based on a Polarity-Controllable Two-Dimensional Transistor.
basic_science · Level V
Where this comes from
- Record sourced from PubMed, PMID 37235483.
- Also identified by DOI 10.1021/acs.nanolett.3c01248.
- No licence information is recorded for this record.
- Because redistribution is not established, this page shows the abstract only. Follow the links below for the full text.
Abstract
Logic-in-memory architecture holds great promise to meet the high-performance and energy-efficient requirements of data-intensive scenarios. Two-dimensional compacted transistors embedded with logic functions are expected to extend Moore's law toward advanced nodes. Here we demonstrate that a WSe<sub>2</sub>/h-BN/graphene based middle-floating-gate field-effect transistor can perform under diverse current levels due to the controllable polarity by the control gate, floating gate, and drain voltages. Such electrical tunable characteristics are employed for logic-in-memory architectures and can behave as reconfigurable logic functions of AND/XNOR within a single device. Compared to the conventional devices like floating-gate field-effect transistors, our design can greatly decrease the consumption of transistors. For AND/NAND, it can save 75% transistors by reducing the transistor number from 4 to 1; for XNOR/XOR, it is even up to 87.5% with the number being reduced from 8 to 1.