Laterally gated ferroelectric field effect transistor (LG-FeFET) using α-In<sub>2</sub>Se<sub>3</sub> for stacked in-memory computing array.
basic_science · Level V
Where this comes from
- Record sourced from PubMed, PMID 37880220.
- Also identified by DOI 10.1038/s41467-023-41991-3 and PMC identifier 10600126.
- No licence information is recorded for this record.
- Because redistribution is not established, this page shows the abstract only. Follow the links below for the full text.
Abstract
In-memory computing is an attractive alternative for handling data-intensive tasks as it employs parallel processing without the need for data transfer. Nevertheless, it necessitates a high-density memory array to effectively manage large data volumes. Here, we present a stacked ferroelectric memory array comprised of laterally gated ferroelectric field-effect transistors (LG-FeFETs). The interlocking effect of the α-In<sub>2</sub>Se<sub>3</sub> is utilized to regulate the channel conductance. Our study examined the distinctive characteristics of the LG-FeFET, such as a notably wide memory window, effective ferroelectric switching, long retention time (over 3 × 10<sup>4 </sup>seconds), and high endurance (over 10<sup>5</sup> cycles). This device is also well-suited for implementing vertically stacked structures because decreasing its height can help mitigate the challenges associated with the integration process. We devised a 3D stacked structure using the LG-FeFET and verified its feasibility by performing multiply-accumulate (MAC) operations in a two-tier stacked memory configuration.