Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures.
basic_science · Level V
Where this comes from
- Record sourced from PubMed, PMID 38326391.
- Also identified by DOI 10.1038/s41467-024-45482-x and PMC identifier 10850082.
- No licence information is recorded for this record.
- Because redistribution is not established, this page shows the abstract only. Follow the links below for the full text.
Abstract
Two-dimensional (2D) semiconductor-based vertical-transport field-effect transistors (VTFETs) - in which the current flows perpendicularly to the substrate surface direction - are in the drive to surmount the stringent downscaling constraints faced by the conventional planar FETs. However, low-power device operation with a sub-60 mV/dec subthreshold swing (SS) at room temperature along with an ultra-scaled channel length remains challenging for 2D semiconductor-based VTFETs. Here, we report steep-slope VTFETs that combine a gate-controllable van der Waals heterojunction and a metal-filamentary threshold switch (TS), featuring a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The integrated TS-VTFETs were realised with efficient current switching behaviours, exhibiting a current modulation ratio exceeding 1 × 10<sup>8</sup> and an average sub-60 mV/dec SS over 6 decades of drain current. The proposed TS-VTFETs with excellent area- and energy-efficiency could help to tackle the performance degradation-device downscaling dilemma faced by logic transistor technologies.