Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer MoS<sub>2</sub> Transistors.
basic_science · Level V
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- Record sourced from PubMed, PMID 39902956.
- Also identified by DOI 10.1021/acs.nanolett.4c01775.
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Abstract
Low-power transistors based on two-dimensional (2D) semiconductors require ultrathin gate insulators, whose atomic layer deposition (ALD) has been difficult without adequate surface preparation. Here, we achieve sub-1 nm equivalent oxide thickness (EOT) on monolayer MoS<sub>2</sub> using HfO<sub>2</sub> and a simple, commonly available Si seed. We first investigate six seed layer candidates (Si, Ge, Hf, La, Gd, Al<sub>2</sub>O<sub>3</sub>) and find that only Si and Ge cause no measurable damage to the MoS<sub>2</sub>. With these, we build monolayer MoS<sub>2</sub> transistors using ALD of HfO<sub>2</sub> top-gate dielectric and find that the Si seed provides the better, low-hysteresis interface. The thickness of this interfacial layer also controls the threshold voltage, enabling normally-off, well-behaved transistors. The thinnest gate stack reached low EOT ≈ 0.9 nm with low leakage (<0.6 μA/cm<sup>2</sup>) and ∼80 mV/dec subthreshold swing at room temperature. This represents a simple top-gate dielectric deposition approach, achievable within many common nanofabrication facilities.