Improved Hysteresis of High-Performance p-Type WSe<sub>2</sub> Transistors with Native Oxide WO<sub><i>x</i></sub> Interfacial Layer.
basic_science · Level V
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- Record sourced from PubMed, PMID 40163025.
- Also identified by DOI 10.1021/acs.nanolett.4c06060.
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Abstract
Atomically thin two-dimensional (2D) semiconductors like transition metal dichalcogenides (TMDs) show great promise as new channel materials for next-generation electronic devices. However, their practical implementation is hampered by the lack of suitable gate dielectrics and interfaces that minimize interface and oxide traps. Here, we introduce a novel strategy to improve the dielectric interface of tungsten diselenide (WSe<sub>2</sub>) p-type field-effect transistors (p-FETs) by integrating a native oxide, tungsten oxide (WO<sub><i>x</i></sub>), as an interlayer into a high-κ hafnium dioxide (HfO<sub>2</sub>) back gate stack. The WO<sub><i>x</i></sub> interlayer serves as both a doping layer to adjust the threshold voltage (<i>V</i><sub>TH</sub>) and an interfacial layer to improve the WSe<sub>2</sub>-HfO<sub>2</sub> interface. The subthreshold swing (SS) in long-channel p-FETs with this gate stack can achieve a near-ideal value (∼68 mV/dec), and hysteresis improves significantly within a 6 V gate sweep range. This work establishes a pathway for high-κ dielectric integration in high-performance 2D electronics.