CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-<i>k</i> Dielectric van der Waals Encapsulation.
basic_science · Level V
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- Record sourced from PubMed, PMID 40178047.
- Also identified by DOI 10.1021/acs.nanolett.5c00220.
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Abstract
Two-dimensional (2D) semiconductors are potential candidates for advanced technology nodes, but their integration with silicon lines remains a significant challenge. Here, we present a high-<i>k</i> dielectric van der Waals encapsulation strategy for the fabrication of 2D semiconductor-based complementary field-effect transistors (CFETs) compatible with established processes. This technique, involving the transfer of a high-<i>k</i> dielectric onto 2D semiconductors, protects channels from polymer contamination, enables O<sub>2</sub> plasma surface cleaning, and facilitates the following dielectric depositions without doping or damage. The strategy results in heterostructures and devices with reduced surface roughness and is applicable to both p- and n-type semiconductors, including MoS<sub>2</sub>, WS<sub>2</sub>, MoTe<sub>2</sub>, and black phosphorus. Utilizing this method, we have successfully fabricated 2D CFET inverters with a gain of up to 19.54 and power consumption as low as 2.63 nW. Our work paves the way for the integration of 2D semiconductors with silicon technology, therefore accelerating the lab-to-fab transition progress.