WSe<sub>2</sub>/SnS<sub>2</sub> Heterostructure Arrays with Bilateral Accumulation Contact for Scalable p-Type Transistors and Logic Circuits.
basic_science · Level V
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- Record sourced from PubMed, PMID 40853732.
- Also identified by DOI 10.1021/acs.nanolett.5c03107.
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Abstract
Field-effect transistors (FETs) based on two-dimensional (2D) materials hold great promise as essential components in next-generation electronics. However, achieving high-performance and large-scale production of p-type 2D FETs has remained a persistent challenge. In this study, SnS<sub>2</sub> is introduced as a tunneling contact layer, and performance-enhanced p-type WSe<sub>2</sub> FET arrays are fabricated by utilizing a self-aligned etching strategy based on WSe<sub>2</sub>/SnS<sub>2</sub> heterojunctions. Owing to the type-III energy band alignment between WSe<sub>2</sub> and SnS<sub>2</sub> forming a bilateral accumulation region at the heterojunction interface, the carrier injection is enhanced into WSe<sub>2</sub> through SnS<sub>2</sub> via a band-to-band tunneling process, which effectively reduces contact resistance and barrier height. The experimental results further demonstrate that, compared with normal WSe<sub>2</sub> FETs, the bilateral accumulation contact FET (BAC-FET) exhibits notable improvements in mobility, on-state current, and on/off ratio. Additionally, various logic circuits, including inverter, NOR, NAND, OR, and AND gates, are realized based on the BAC-FET arrays.