Noninvasive van der Waals Interface Integrations for Intrinsic 2D Semiconductor Characterization.
basic_science · Level V
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- Record sourced from PubMed, PMID 40994232.
- Also identified by DOI 10.1021/acs.nanolett.5c03799.
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Abstract
"Plug-and-probe" van der Waals (vdW) integration preserves surfaces of low-dimensional semiconductors but suffers from interfacial charge transfer and weak electrostatic control at the dielectric-channel heterointerface, underestimating intrinsic optical and electrical properties. We introduce a MoS<sub>2</sub>-assisted noninvasive vdW integration method, achieving 94% intrinsic property expression. Controlled defect engineering on MoS<sub>2</sub> creates sulfur vacancies and dangling bonds, enabling uniform atomic layer deposition (ALD) of high-κ HfO<sub>2</sub> dielectrics. This resolves interfacial charge issues from conventional metal oxidation. Simultaneously, the ALD dielectric adsorbs onto source/drain contacts, eliminating the inner spacer in prior half-gate "plug-and-probe" structures. The fabricated monolayer MoS<sub>2</sub> transistor arrays demonstrate exceptional performance with on-state current densities exceeding 10<sup>-6</sup> A μm<sup>-1</sup>, a subthreshold swing of 79 mV decade<sup>-1</sup>, and an on/off current ratio of more than 10<sup>8</sup>, surpassing those of all reported "plug-and-probe" devices. The transistors maintain >90% initial performance after 200 °C annealing and ambient storage for 60 days, confirming their exceptional thermal and temporal stability.