Enhancing Gate Control and Mitigating Short Channel Effects in 20-50 nm Channel Length Amorphous Oxide Thin-Film Transistors.

Abstract

Field-effect transistors (FETs) with single-gates are adversely affected by short channel effects such as drain-induced barrier lowering (DIBL) and increases in the magnitude of subthreshold swing as the channel length is reduced. Dual-gate and gate-all-around geometries are often employed to improve gate control in very short channel length transistors. This can introduce significant process complexity to the device fabrication compared to that of single-gate transistors. It is shown in this paper that substantial reductions in short channel effects are possible in single-gate FETs with indium gallium zinc oxide semiconductor channels by modifying the design of the source and drain electrodes to possess an array of tapered tips that are designated as nanospike electrodes. FETs with channel lengths of 20-25 nm and nanospike electrodes have DIBL and other key metrics that are comparable to those in much larger (70-80 nm) channel length FETs with a conventional source/drain electrode design. These improvements stem from better gate control near the source and drain electrode tips due to the shape of these electrodes. These bottom-gate FETs had a gate insulator consisting of a 9 nm thick Al₂O₃ and independent Ni gates. This design approach is expected to be very helpful for a variety of semiconductor technologies being considered for back-end-of-line applications. Simulations with Synopsys Sentaurus were performed to understand the device physics of these FETs and facilitate a more detailed comparison.