High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems.
basic_science · Level V
Where this comes from
- Record sourced from PubMed, PMID 41290656.
- Also identified by DOI 10.1038/s41467-025-66770-0 and PMC identifier 12749465.
- Licence recorded as CC BY-NC-ND.
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Abstract
The integration of high-κ dielectrics with two-dimensional (2D) semiconductors has long been limited by the low reactivity of their dangling-bond-free surfaces and the scalability issues of conventional deposition techniques. Here, we report a universal van der Waals (vdW) integration strategy using HfSe<sub>2</sub> as a high-κ precursor that is dry-transferred onto MoS<sub>2</sub> and WSe<sub>2</sub> and fully converted into amorphous HfO<sub>2</sub> via plasma oxidation, while preserving atomically flat vdW interfaces. The resulting HfO<sub>2</sub>/MoS<sub>2</sub> and HfO<sub>2</sub>/WSe<sub>2</sub> gate stacks exhibit suppressed interface trap densities (D<sub>it</sub> ≈ 7-8 × 10<sup>10 </sup>cm<sup>-2</sup> eV<sup>-1</sup>) and high dielectric constants (κ ≈ 23). MoS<sub>2</sub> n-type field-effect transistors (nFETs) and WSe<sub>2</sub> p-type field-effect transistors (pFETs) fabricated with this approach achieve nearly ideal subthreshold swing ( ≈ 60 mV/dec) and negligible hysteresis ( ≈ 3 mV). This scalable methodology enables the vertical integration of complementary logic, demonstrated by complementary FET inverters and ring oscillators, establishing a promising route toward three-dimensional, energy-efficient logic technologies.