Room-Temperature Fabricated Edge-Contact Carbon Nanotube Field-Effect Transistors: A Solution to Electrostatic Screening.

Abstract

Extensive research has established carbon nanotube (CNT) field-effect transistors (FETs) as promising candidates for sub-1 nm technology nodes owing to their demonstrated advantages in speed and power consumption. Additionally, breakthroughs in CNT film density have effectively increased the driving current. However, this density scaling triggers severe electrostatic screening at conventional side-contact structure and gate electrodes, forcing a fundamental trade-off between performance and materials density. To address this bottleneck, we developed a technology for fabricating edge-contact CNT FETs at room temperature. The as-prepared FETs exhibit linear scaling of on-state current (<i>I</i>_on) with CNT layer count, thereby experimentally demonstrating that the edge-contact structure can effectively suppress the electrostatic screening at the contact. Further, an air-gate structure that well matches the edge-contact fabrication process was introduced to form the dual-gate edge-contact FETs, which reduces the subthreshold swing (SS) of the bilayer CNT film edge-contact FETs from 207 to 68 mV/dec and boosts the on/off current ratio from 5 × 10⁴ to >10⁶. Meanwhile, as the channel length was scaled to 1 μm, the <i>I</i>_on of the dual-gate edge-contact FETs increased to 43 μA/μm. Remarkably, the quasi-0D edge-contact and dual-gate structure can retain the electrical performance after 10 months of ambient exposure without passivation. This work provides an electrostatic screening solution for high-density CNT electronics, and the room-temperature edge-contact fabrication process significantly reduces thermal budgets particularly critical for integrated circuits, three-dimensional integrated circuits (3D-ICs), and flexible nanoelectronics.