van der Waals dielectrics for threshold engineering in two-dimensional field effect transistors.
basic_science · Level V
Where this comes from
- Record sourced from PubMed, PMID 41698936.
- Also identified by DOI 10.1038/s41467-026-69089-6 and PMC identifier 13022202.
- Licence recorded as CC BY-NC-ND.
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Abstract
Two-dimensional (2D) semiconductors are promising for next-generation field-effect transistors (FETs), but their integration into complementary-metal-oxide-semiconductors (CMOS) logic is hindered by improper threshold voltages ( <math xmlns="http://www.w3.org/1998/Math/MathML"> <msub><mrow><mi>V</mi></mrow> <mrow><mi>t</mi> <mi>h</mi></mrow> </msub> </math> ), leading to excessive power consumption. While past efforts have focused on improving gate electrostatics and near-ideal subthreshold swing ( <math xmlns="http://www.w3.org/1998/Math/MathML"><mi>S</mi> <mi>S</mi></math> ), systematic <math xmlns="http://www.w3.org/1998/Math/MathML"> <msub><mrow><mi>V</mi></mrow> <mrow><mi>t</mi> <mi>h</mi></mrow> </msub> </math> engineering in 2D FETs remains unexplored. Here, we investigate high-κ van der Waals (vdW) dielectrics including metal oxyhalides such as LaOBr, BiOBr, and BiOCl, and bimetallic thiophosphates such as LiInP<sub>2</sub>S<sub>6</sub> (LIPS), LiInP<sub>2</sub>Se<sub>6</sub> (LIPSe) and CuInP<sub>2</sub>S<sub>6</sub> (CIPS), and demonstrate that bimetallic thiophosphates enable programmable and non-volatile <math xmlns="http://www.w3.org/1998/Math/MathML"> <msub><mrow><mi>V</mi></mrow> <mrow><mi>t</mi> <mi>h</mi></mrow> </msub> </math> tuning in both n-type monolayer MoS<sub>2</sub> and p-type bilayer WSe<sub>2</sub> FETs. Leveraging ion-mediated <math xmlns="http://www.w3.org/1998/Math/MathML"> <msub><mrow><mi>V</mi></mrow> <mrow><mi>t</mi> <mi>h</mi></mrow> </msub> </math> tuning, we realize 2D CMOS inverters with nearly three orders of magnitude reduction in static power while maintaining high switching speed. Combining experiments with industry-compatible SPICE modeling, we identify an optimal <math xmlns="http://www.w3.org/1998/Math/MathML"> <msub><mrow><mi>V</mi></mrow> <mrow><mi>t</mi> <mi>h</mi></mrow> </msub> </math> window that minimizes power with negligible delay overhead, enabling built-in power gating and improved power-performance-area metrics without additional sleep transistors.