Micro-LED/van der Waals heterointegration for in-pixel processing display architecture.
basic_science · Level V
Where this comes from
- Record sourced from PubMed, PMID 41723110.
- Also identified by DOI 10.1038/s41467-026-69786-2 and PMC identifier 13039472.
- Licence recorded as CC BY.
- The licence permits redistribution, so the abstract is shown in full and the full text is available from the publisher.
Abstract
The rapid evolution of intelligent display technologies is driving the development of next-generation edge smart systems, yet conventional off-pixel processing architectures suffer from severe display latency and energy bottlenecks. Embedding in-memory computing features into pixel-level active drivers presents a promising strategy for co-locating image processing and display. In this work, we provide an in-pixel processed display-driven architecture that integrates micro-LEDs with MoS<sub>2</sub> in-memory transistors into a 16 × 16 active display array. Our in-pixel processing design exhibits high luminance (>3 × 10<sup>5 </sup>cd·m⁻<sup>2</sup>), high-speed operation (5000 Hz), and compact dimensions of 20 × 35 μm per pixel. Crucially, leveraging the segmented voltage-luminance response and the non-volatile multilevel conductance update characteristics of the design devices, we demonstrate in-situ image reconstruction and real-time display using in-pixel processed micro-LED arrays. The image reconstruction capability of the proposed design is validated through a neural network-based image recognition task, where the inference process is implemented directly on the pixel array by deploying the trained weights via non-volatile conductance modulation. The reconstructed images achieved a significantly higher accuracy of 99.29% compared to the original inputs (79.81%). These results highlight the significance of the in-pixel processed display architecture as a promising approach to realize high-performance intelligent display technologies.