Nonvolatile Sequential Logic Enabled by CuInP<sub>2</sub>S<sub>6</sub> van der Waals Ferroelectric Field-Effect Transistors.

Lee, Hanwool; Kang, Junzhe; Lin, Ye; Xu, Xiaotong; Zhao, Zijing; Ryu, Hojoon; Tunga, Ashwin; Shukla, Ankit et al. · ACS Nano · 2026

basic_science · Level V

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Abstract

Nonvolatile flip-flops and latches have been proposed as key building blocks for improving the reliability and energy efficiency of computing systems operating under aggressive power gating and intermittent power availability. Ferroelectric field-effect transistors (FeFETs) based on van der Waals (vdW) heterostructures provide a promising approach for nonvolatile sequential logic by enabling direct integration of memory functionality into logic devices while minimizing interface-related degradation. In this work, CuInP<sub>2</sub>S<sub>6</sub>-based vdW FeFETs are fabricated in both metal-ferroelectric-metal-insulator-semiconductor and metal-ferroelectric-semiconductor configurations, exhibiting robust ferroelectric switching and stable nonvolatile behavior. Building on these devices, ferroelectric nonvolatile inverters are realized, followed by a nonvolatile ferroelectric latch that reliably restores its logic state after complete power loss. The proposed latch leverages ambipolar MoTe<sub>2</sub> channels to inherently drive the FeFET gate-source and gate-drain voltages to full rail-to-rail values (<i>V</i><sub>GS</sub> = <i>V</i><sub>GD</sub> = ±<i>V</i><sub>DD</sub>) in a state-dependent manner, thereby ensuring reliable polarization switching without auxiliary sensing circuitry or additional bias-management schemes. Owing to the clean vdW interfaces and intrinsic circuit operation, the latch restores its state upon power recovery using only simple control signals. These results demonstrate the strong performance of 2D vdW FeFETs and establish nonvolatile latch operation as a viable experimental platform for nonvolatile sequential logic and energy-efficient computing architectures.