Wafer-scale 2D MoS₂ transistors with self-aligned angstrom gate length and nanometer channel length.

Abstract

As conventional silicon scaling approaches fundamental physical limits, two-dimensional semiconductors offer a promising pathway for continued transistor miniaturization. Here we show an ultra-scaled vertical MoS₂ transistor that combines a sub-1 nm gate and a 10 nm channel length, realized through a dual-self-aligned fabrication strategy. In this architecture, the exposed edge of a monolayer graphene at etched sidewalls serves as an atomically thin gate electrode, while the sidewalls also act as self-aligned masks for defining an ultra-short MoS₂ channel through oblique-angle deposition. This co-scaling strategy yields an on-state current density of 23 μA/μm and on/off current ratio exceeding 10⁶. Systematic device simulations further elucidate the electrostatic control, effective gate length, and tunneling-limited scaling behavior of this vertical architecture. Beyond individual transistors, we demonstrate wafer-scale arrays and their integration into logic circuits (inverters, NAND, NOR gates), underscoring the scalability and integration potential of this platform.