High-Mobility and Reliability Ultra-Thin-Channel Oxide Semiconductor Field-Effect Transistors for Chip-Interconnect-Embedded Logic and Ferroelectric Memory.

Abstract

Logic and memory transistors integrated with oxide semiconductors are promising for monolithic 3D systems that enable reconfigurable functionality and enhanced on-chip communication. However, challenges in controlling carrier mobility, carrier concentration, and defect density have hindered their deployment in advanced chip technologies. Here, we report a heterojunction oxide semiconductor channel approach that mitigates the interface/channel defect density and achieves field-effect mobility to >100 cm²/V.s, competitive with thin-film silicon channels. By engineering a bilayer oxide channel, we demonstrate a low-thermal-budget, ultra-scaled, memory-logic dual-mode ferroelectric transistor that exhibits a high on-state current of 800 µA/µm at V_d = 1 V, a positive threshold voltage, and excellent reliability with only 30 mV threshold shift after 5000s of gate-bias stress. Furthermore, it exhibits robust memory endurance exceeding 10⁷ cycles and a fast ferroelectric read-after-write delay of 180 ns. TCAD simulation (Ginestra) reveals that performance improvement is attributed to the defect self-compensation effect in bilayer channel, which stabilizes disordered metal bonds and weakly bonded oxygen states. This work establishes a pathway towards reliable, high-performance oxide-based transistors, offering a scalable solution for next-generation low-power reconfigurable chips tailored for generative artificial intelligence.